1. Field of the Invention
The present invention relates to data-outputting buffer circuits and, more particularly, to data-outputting buffer circuits suitable for reducing noise which is generated in an output buffer circuit part when minus electric filed is applied to a data output pad in inputting data.
2. Discussion of the Related Art
Buffer is a temporary memory spot where data are received and transmitted between two apparatuses or two programs having different rates and different units for processing data. It functions as a gate delaying signal transmission in logic circuits temporarily.
In semiconductor memory devices, a data-outputting buffer circuit serves to output data read from a memory cell to an external chip. Applied to semiconductor memory devices with high integration and high speed operations, it accompanies noise in operation of outputting data. One of main reasons for noise is big peak current which is generated when a big-sized transistor placed in output terminal of the data-outputting buffer circuit performs shift operation.
A conventional data-outputting buffer circuit will be discussed with reference to the accompanying drawings.
As shown in FIG. 1, a conventional data-outputting buffer circuit is structured to include a pullup transistor 2 and a pulldown transistor 3 which are serially connected to each other and have both source and drain connected to an input/output pad 1, a clamp transistor 4 having a gate electrode connected to a Vss terminal and a drain electrode connected to the gate electrode of the pullup transistor 2, a first driving part 5 composed of a PMOS M5 and an NMOS M4 serially connected to each other, and connected to the pullup transistor 2 through a noise-reducing resistor R1 for driving the pullup transistor 2, a second driving part 6 connected to the gate electrode of the pulldown transistor 3 through a noise-reducing resistor R2 for driving the pulldown transistor 3, and an input buffer 7 connected to the input/output pad 1 for inputting data.
The drain electrode of the pullup transistor 2 is connected to the Vcc terminal and the source electrode of the clamp transistor 4 is connected to both the input/output pad 1 and the drain electrode of the pulldown transistor 3. The second driving part 6 is composed of an inverter for inverting DOUT signals and then applying them to the pulldown transistor 3.
A data-outputting buffer circuit having the foregoing structure uses the input/output pad 1 for both inputting and outputting data.
When a data of a low level, that is, 0.8 -1V as for a fDRAM, is applied through the input/output pad 1, minus electric field is applied so that a voltage is generated between the gate electrode and source electrode of the pullup transistor (M2) 2. It is because the gate electrode of the pullup transistor 2 has ground potential GND. If the gate and source voltage of the pullup transistor 2 is bigger than V.sub.T, the pullup transistor 2 is turned on. At this time, since big is the difference of the voltages of the source and drain of the pullup transistor 2, there is generated hot carrier in a channel region so that current flows toward substrate potential V.sub.BB of the pullup transistor 2 to heighten the potential of the substrate bias. The clamp transistor 4 serves to prevent the increase of the potential of the substrate bias.
Since the output buffer should keep high impedance while data is being transmitted or received, the gate electrodes of the pullup and pulldown transistors 2 and 3 should keep the ground potential GND. In other words, the DOUT signal keeps a high level.
When the clamp transistor 4, turned on by minus potential applied to the input/output pad 1, discharges charge accumulated in the gate electrode of the pullup transistor 2 toward the input/output pad 1, the charge is again supplied from the source electrode of the first driving part 5 to the gate electrode of the pullup transistor 2, thereby generating noise. To restrain noise, a resistor R1 serves to reduce noise.
Since potential difference between the gate and source of the pullup transistor 2 can be reduced when the level of minus voltage of the input/output pad 1 is declined to the threshold voltage of the clamp transistor 4, temporary turn-on of the pullup transistor 2 can not be prevented.
When the clamp transistor 4, turned on by minus potential applied to the input/output pad 1, discharges charge accumulated in the gate electrode of the pullup transistor 2 toward the input/output pad 1, the charge is again supplied from the source electrode of the NMOS M4 of the first driving part 5 to the gate electrode of the pullup transistor 2 so that the resistor R1 delays the charge accumulating time of the gate electrode of the pullup transistor 2 in outputting data, thereby causing the delay of pull-up operation. Therefore, there can not be effectively refrained noise which is generated by the increase of potential of the substrate bias generated due to a big difference between the drain and source of the pullup transistor 2.